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1 features ? incorporates the arm7tdmi ? arm ? thumb ? processor core ? high-performance 32-bit risc architecture ? high-density 16-bit instruction set ? leader in mips/watt ? embedded ice (in-circuit emulation) 136k bytes of on-chip sram ? 32-bit data bus, single-clock cycle access 512k words 16-bit flash memory (8 mbits) ? single voltage read/write, 110 ns access time ? sector erase architecture ? fast word program time of 20 s; fast sector erase time of 200 ms ? dual-plane organization allows concurrent read and program/erase ? erase suspend capability ? low-power operation: 25 ma active, 10 a standby ? data polling, toggle bit and ready/busy end of program cycle detection ? reset input for device initialization ? sector program unlock command ? factory-programmed at91 flash uploader software fully programmable external bus interface (ebi) ? up to 8 chip selects, maximum external address space of 64m bytes ? software programmable 8/16-bit external data bus 8-level priority, individually maskable, vectored interrupt controller ? 4 external interrupts, including a high-priority low-latency interrupt request 32 programmable i/o lines 3-channel 16-bit timer/counter ? 3 external clock inputs ? 2 multi-purpose i/o pins per channel 2usarts ? 2 dedicated peripheral data controller (pdc) channels per usart programmable watchdog timer advanced power-saving features ? cpu and peripherals can be de-activated individually fully static operation: ? 0 hz to 33 mhz internal frequency range at 3.0v, 85 c 2.7v to 3.6v operating range -40 cto85 c temperature range available in a 120-ball bga package description the at91fr4081 is a member of the atmel at91 16/32-bit microcontroller family, which is based on the arm7tdmi processor core. the processor has a high-perfor- mance 32-bit risc architecture with a high-density 16-bit instruction set and very low power consumption. in addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. the eight-level priority-vectored interrupt controller, together with the peripheral data controller, significantly enhance real-time device performance. by combining the microcontroller, featuring more than 1 mbit of on-chip sram and a wide range of peripheral functions, with 8 mbits of flash memory in a single compact 120-ball bga package, the atmel at91fr4081 provides a powerful, flexible and cost- effective solution to many compute-intensive embedded control applications and offers significant board size and system cost reductions. the flash memory may be programmed via the jtag/ice interface or the factory-pro- grammed flash uploader using a single device supply, making the at91fr4081 ideal for in-system programmable applications. at91 arm ? thumb ? microcontrollers at91fr4081 rev. 1386c?atarm?02/02
2 at91fr4081 1386c?atarm?02/02 pin configuration figure 1. at91fr4081 pinout (top view) gnd p26 ncs2 ncs0 tck tdo p25 mcko mcki p22 rxd1 p21/txd1 ntri gnd p27 ncs3 ncs1 nwait tdi vdd gnd vdd p18 p20 sck1 vdd a0 nlb tms p24 bms nwodvf nwr1 nub p13 sck0 p17 p16 p15 rxd0 p19 vdd p23 nrst p12 fiq p11 irq2 p14 txd0 gnd p10 irq1 gnd p9 irq0 p8 tiob2 vdd vdd gnd p30/a22 cs5 p6 tclk2 p5 tiob1 p7 tioa2 gnd p29/a21 cs6 p31/a23 cs4 p0 tclk0 p4 tioa1 p3 tclk1 a1 gnd vdd vdd gnd p2 tiob0 ncsf nrd noe vdd gnd vdd a2 gnd d0 d8 p1 tioa0 a3 a4 d2 d9 d1 a5 a6 a7 d11 d3 d10 a8 a18 vpp d5 d12 d4 a19 nbusy p28/a20 cs7 d14 vdd nc d6 gnd vdd nrstf nwr0 nwe a9 a10 gnd d15 d7 nc d13 gnd a11 a12 a13 vdd vdd a17 gnd vdd nc nc a14 a16 a15 gnd kjhgfedcba 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
3 at91fr4081 1386c ? atarm ? 02/02 pin description table 1 . at91fr4081 pin description module name function type active level comments ebi a0 - a23 address bus output ? valid after reset d0 - d15 data bus i/o ? ncs0 - ncs3 external chip select output low used to select external devices cs4 - cs7 external chip select output high a23 - a20 after reset nwr0 lower byte 0 write signal output low used in byte write option nwr1 upper byte 1 write signal output low used in byte write option nrd read signal output low used in byte write option nwe write enable output low used in byte select option noe output enable output low used in byte select option nub upper byte select output low used in byte select option nlb lower byte select output low used in byte select option nwait wait input input low bms boot mode select input ? sampledduringreset;mustbedrivenlow during reset for flash to be used as boot memory aic fiq fast interrupt request input ? pio-controlled after reset irq0 - irq2 external interrupt request input ? pio-controlled after reset timer tclk0 - tclk2 timer external clock input ? pio-controlled after reset tioa0 - tioa2 multi-purpose timer i/o pin a i/o ? pio-controlled after reset tiob0 - tiob2 multi-purpose timer i/o pin b i/o ? pio-controlled after reset usart sck0 - sck1 external serial clock i/o ? pio-controlled after reset txd0 - txd1 transmit data output output ? pio-controlled after reset rxd0 - rxd1 receive data input input ? pio-controlled after reset pio p0 - p31 parallel io line i/o ? wd nwdovf watchdog overflow output low open drain clock mcki master clock input input ? schmidt trigger mcko master clock output output ? reset nrst hardware reset input input low schmidt trigger ntri tri-state mode select input low sampled during reset ice tms test mode select input ? schmidt trigger, internal pull-up tdi test data input input ? schmidt trigger, internal pull-up tdo test data output output ? tck test clock input ? schmidt trigger, internal pull-up
4 at91fr4081 1386c ? atarm ? 02/02 flash memory ncsf flash memory select input low enables flash memory when pulled low nbusy flash memory busy output output low flash rdy/busy signal; open-drain nrstf flash memory reset input input low resets flash to standard operating mode power v dd power power ? all v dd and all gnd pins must be connected to their respective supplies by the shortest route gnd ground ground ? vpp faster program/erase voltage power ? see at49bv/lv8011(t) 8-megabit (512k x 16/1m x 8) 3-volt only flash memory datasheet table 1 . at91fr4081 pin description (continued) module name function type active level comments
5 at91fr4081 1386c ? atarm ? 02/02 block diagram figure 2. at91fr4081 ebi: external bus interface ram 8k bytes asb controller clock amba bridge ebi user interface pio: parallel i/o controller d0-d15 a1-a19 a0/nlb nrd/noe nwr0/nwe nwr1/nub nwait ncs0 ncs1 p26/ncs2 p27/ncs3 p29/a21/cs6 p30/a22/cs5 p31/a23/cs4 mcki p25/mcko p12/fiq p9/irq0 p10/irq1 p11/irq2 p13/sck0 p14/txd0 p15/rxd0 p20/sck1 p21/txd1/ntri p22/rxd1 p16 p17 p18 p19 p23 p24/bms reset nrst wd: watchdog timer nwdovf p i o tc: timer counter tc0 tc1 p0/tclk0 p3/tclk1 p6/tclk2 p1/tioa0 p2/tiob0 p4/tioa1 p5/tiob1 tc2 p7/tioa2 p8/tiob2 aic: advanced interrupt controller usart0 usart1 2 pdc channels 2 pdc channels ps: power saving apb chip id p i o a1 - a20 d0 - d15 ncsf vdd vdd vdd nrstf nbusy oe we vpp gnd ce vcc vccq byte reset rdy/busy vpp gnd mcu at91m40800 flash memory at49bv1604/1614 arm7tdmi core asb tms tdo tdi tck embedded ice vdd gnd p28/a20/cs7
6 at91fr4081 1386c ? atarm ? 02/02 architectural overview the at91fr4081 integrates atmel ? s at91r40807 arm thumb processor and an at49bv/lv8011 8-mbit flash memory die in a single compact 120-ball bga device. the address, data and control signals, except the flash memory enable, are internally interconnected. the at91r40807 architecture consists of two main buses, the advanced system bus (asb) and the advanced peripheral bus (apb). desi gned for maximum performance and controlled by the memory controller, the asb interfaces the arm7tdmi processor with the on-chip 32-bit memories, the external bus interface (ebi) and the amba ? bridge. the amba bridge drives the apb, which is designed for accesses to on-chip peripherals and optimized for low power consumption. the at91fr4081 implements the ice port of the arm7tdmi processor on dedicated pins, offering a complete, low-cost and easy-to-use debug solution for target debugging. memories the at91fr4081 embeds 136k bytes of internal sram. the internal memory is directly con- nected to the 32-bit data bus and is single-cycle accessible. this provides maximum performance of 36 mips at 40 mhz by using the arm instruction set of the processor, mini- mizing system power consumption and improving on the performance of separate memory solutions. the at91fr4081 features an external bus interface (ebi), which enables connection of external memories and application-specific peripherals. the ebi supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. the ebi implements the early read protocol, enabling faster memory accesses than standard memory interfaces. the at91fr4081 embeds a flash memory organized as 512k 16-bit words, accessed via the ebi. its main function is as a program memory. a 16-bit thumb instruction can be loaded from flash memory in a single access. separate mcu and flash memory reset inputs (nrst and nrstf) are provided for maximum flexibility. the user is thus free to tailor the reset operation to the application. the at91fr4081 integrates resident boot software called at91 flash uploader software. the at91 flash uploader software is able to upload program application software into its flash memory. peripherals the at91fr4081 integrates several peripherals, which are classified as system or user peripherals. all on-chip peripherals are 32-bit accessible by the amba bridge, and can be programmed with a minimum number of instructions. the peripheral register set is composed of control, mode, data, status and enable/disable/status registers. an on-chip peripheral data controller (pdc) transfers data between the on-chip usarts and on- and off-chip memories address space without processor intervention. most importantly, the pdc removes the processor interrupt handling overhead, making it possible to transfer up to 64k contiguous bytes without reprogramming the start address, thus increasing the perfor- mance of the microcontroller, and reducing the power consumption. system peripherals the external bus interface (ebi) controls the external memory or peripheral devices via an 8- or 16-bit databus and is programmed through the apb. each chip select line has its own pro- gramming register. the power-saving (ps) module implements the idle mode (arm7tdmi core clock stopped until the next interrupt) and enables the user to adapt the power consumption of the microcon- troller to application requirements (independent peripheral clock control). the advanced interrupt controller (aic) controls the internal interrupt sources from the inter- nal peripherals and the four external interrupt lines (including the fiq) to provide an interrupt
7 at91fr4081 1386c ? atarm ? 02/02 and/or fast interrupt request to the arm7tdmi. it integrates an 8-level priority controller, and, using the auto-vectoring feature, reduces the interrupt latency time. the parallel input/output controller (pio) controls up to 32 i/o lines. it enables the user to select specific pins for on-chip peripheral input/output functions, and general-purpose input/output signal pins. the pio controller can be programmed to detect an interrupt on a sig- nal change from each line. the watchdog (wd) can be used to prevent system lock-up if the software becomes trapped in a deadlock. the special function (sf) module integrates the chip id, the reset status and the protect registers. user peripherals two usarts, independently configurable, enable communication at a high baud rate in syn- chronous or asynchronous mode. the format includes start, stop and parity bits and up to 8 data bits. each usart also features a timeout and a time guard register, facilitating the use of the two dedicated peripheral data controller (pdc) channels. the 3-channel, 16-bit timer counter (tc) is highly programmable and supports capture or waveform modes. each tc channel can be programmed to measure or generate different kinds of waves, and can detect and control two input/output signals. the tc has also 3 exter- nal clock signals.
8 at91fr4081 1386c ? atarm ? 02/02 associated documentation table 2 . associated documentation product information document title at91fr4081 internal architecture of processor arm/thumb instruction sets embedded in-circuit-emulator arm7tdmi (thumb) datasheet external memory interface mapping peripheral operations peripheral user interfaces at91x40 series datasheet dc characteristics power consumption thermal and reliability considerations ac characteristics at91r40807 electrical characteristics product overview ordering information packaging information soldering profile at91fr4081 summary datasheet (this document)
9 at91fr4081 1386c ? atarm ? 02/02 product overview power supply the at91fr4081 has a single power supply pin, vdd. the vdd pin supplies the i/o pads and the core. the supported voltage range on vdd is 2.7v to 3.6v. input/output considerations the at91fr4081 i/o pads accept voltage levels up to the power supply limit. after the reset, the microcontroller peripheral i/os are initialized as inputs to provide the user with maximum flexibility. it is recommended that in any application phase, the inputs to the microcontroller be held at valid logic levels to minimize the power consumption. master clock the at91fr4081 has a fully static design and works on the master clock (mck), provided on the mcki pin from an external source. the master clock is also provided as an output of the device on the pin mcko, which is multi- plexed with a general purpose i/o line. while nrst is active, and after the reset, the mcko is valid and outputs an image of the mck signal. the pio controller must be programmed to use this pin as standard i/o line. reset reset restores the default states of the user interface registers (defined in the user interface of each peripheral), and forces the arm7tdmi to perform the next instruction fetch from address zero. except for the program counter the arm7tdmi registers do not have defined reset states. nrst pin nrst is active low-level input. it is asserted asynchronously, but exit from reset is synchro- nized internally to the mck. the signal presented on mcki must be active within the specification for a minimum of 10 clock cycles up to the rising edge of nrst to ensure correct operation. the first processor fetch occurs 80 clock cycles after the rising edge of nrst. watchdog reset the watchdog can be programmed to generate an internal reset. in this case, the reset has the same effect as the nrst pin assertion, but the pins bms and ntri are not sampled. boot mode and tri-state mode are not updated. if the nrst pin is asserted and the watchdog trig- gers the internal reset, the nrst pin has priority. emulation functions tri-state mode the at91fr4081 provides a tri-state mode, which is used for debug purposes in order to connect an emulator probe to an application board. this feature can also be used to program the embedded flash within a standard nvm programmer. in tri-state mode, all the output pin drivers of the microcontroller are disabled. to enter tri- state mode, the pin ntri must be held low during the last 80 clock cycles before the rising edge of nrst. for normal operation, the pin ntri must be held high during reset by a resistor of up to 400k ohm. ntri is multiplexed with i/o line p21 and usart1 serial data transmit line txd1. stan- dard rs232 drivers generally contain internal 400k ohm pull-up resistors. if txd1 is connected to a device not including this pull-up, the user must make sure that a high level is tied on ntri while nrst is asserted. jtag/ice debug arm standard embedded in-circuit emulation is supported via the jtag/ice port. the pins tdi, tdo, tck and tms are dedicated to this debug function and can be connected to a host computer via the external ice interface. in ice debug mode, the arm7tdmi core responds
10 at91fr4081 1386c ? atarm ? 02/02 with a non-jtag chip id that identifies the microcontroller. this is not fully ieee1149.1 compliant. memory controller the arm7tdmi processor address space is 4g bytes. the memory controller decodes the internal 32-bit address bus and defines three address spaces: internal memories in the four lowest megabytes middle space reserved for the external devices (memory or peripherals) controlled by the ebi internal peripherals in the four highest megabytes in any of these address spaces, the arm7tdmi operates in little-endian mode only. internal memories the at91fr4081 integrates 8k bytes of primary internal sram that is 32 bits wide and sin- gle-clock cycle accessible. this memory bank is mapped at address 0x0 (after the remap command), allowing arm7tdmi exception vectors between 0x0 and 0x20 to be modified by the software. the rest of the bank can be used for stack allocation (to speed up context saving and restoring), or as data and program storage for critical algorithms. byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one cycle. fetching thumb or arm instructions is supported and internal memory can store twice as many thumb instructions as arm ones. the at91fr4081 also integrates an extended memory bank of 128k bytes at address 0x0010 0000. placing the sram on-chip and using the 32-bit data bus bandwidth maximizes the microcontroller performance and minimizes the system power consumption. the 32-bit bus increases the effectiveness of the use of the arm instruction set, and the ability of processing data that is wider than 16-bit, thus making optimal use of the arm7tdmi advanced performance. being able to dynamically update application software in the 128-kbyte sram adds an extra dimension to the at91fr4081. in order to prevent accidental write to the extended sram while the application is running, a write detection feature has been implemented. the at91fr4081 also integrates a 1-mbyte flash memory that is accessed via the external bus interface. all data, address and control lines, except for the chip select signal, are con- nected within the device. byte and half-word accesses are supported. boot mode select the arm reset vector is at address 0x0. after the nrst line is released, the arm7tdmi exe- cutes the instruction stored at this address. this means that this address must be mapped in nonvolatile memory after the reset. the input level on the bms pin during the last 10 clock cycles before the rising edge of the nrst selects the type of boot memory (see table 1). if the embedded flash memory is to be used as boot memory, the bms input must be pulled down externally. the pin bms is multiplexed with the i/o line p24 that can be programmed after reset like any standard pio line. remap command the arm vectors (reset, abort, data abort, prefetch abort, undefined instruction, interrupt, fast interrupt) are mapped from address 0x0 to address 0x20. in order to allow these vectors to be redefined dynamically by the software, the at91fr4081 uses a remap command that enables switching between the boot memory and the internal primary sram bank addresses. table 3 . boot mode select bms boot memory 1 internal 32-bit extended sram 0 external 16-bit memory on ncs0
11 at91fr4081 1386c ? atarm ? 02/02 the remap command is accessible through the ebi user interface by writing one in rcb of ebi_rcr (remap control register). performing a remap command is mandatory if access to the other external devices (connected to chip selects 1 to 7) is required. the remap operation can only be changed back by an internal reset or an nrst assertion. abort control the abort signal providing a data abort or a prefetch abort exception to the arm7tdmi is asserted when accessing an undefined address in the ebi address space. no abort is generated when reading the internal memory or by accessing the internal peripher- als, whether the address is defined or not. external bus interface the external bus interface handles the accesses between addresses 0x0040 0000 and 0xffc0 0000. it generates the signals that control access to the external devices, and can be configured from eight 1-mbyte banks up to four 16-mbyte banks. it supports byte, half-word and word aligned accesses. for each of these banks, the user can program: number of wait states number of data float times (wait time after the access is finished to prevent any bus contention in case the device is too long in releasing the bus) data bus width (8-bit or 16-bit) with a 16-bit wide data bus, the user can program the ebi to control one 16-bit device (byte access select mode) or two 8-bit devices in parallel that emulate a 16-bit memory (byte write access mode). the external bus interface features also the early read protocol, configurable for all the devices, that significantly reduces access time requirements on an external device in the case of single-clock cycle access. in the at91fr4081, the external bus interface connects internally to the flash memory. flash memory the 8-mbit flash memory is organized as 524,288 words of 16 bits each. the flash memory is addressed as 16-bit words via the ebi. it uses address lines a1 - a19. the address, data and control signals, except the flash memory enable, are internally inter- connected. the user should connect the flash memory enable (ncsf) to one of the active- low chip selects on the ebi; ncs0 must be used if the flash memory is to be the boot mem- ory. in addition, if the flash memory is to be used as boot memory, the bms input must be pulled down externally in order for the processor to perform correct 16-bit fetches after reset. during boot, the ebi must be configured with correct number of standard wait states. for example, five standard wait states are required when the microcontroller is running at 40 mhz. the user must ensure that all vdd and all gnd pins are connected to their respective sup- plies by the shortest route. the flash memory powers-on in the read mode. command sequences are used to place the device in other operating modes, such as program and erase. a separate flash memory reset input pin (nrstf) is provided for maximum flexibility, enabling the reset operation to adapt to the application. when this input is at a logic high level, the memory is in its standard operating mode; a low level on this input halts the current mem- ory operation and puts its outputs in a high impedance state. the flash memory features data polling to detect the end of a program cycle. while a program cycle is in progress, an attempted read of the last word written will return the complement of the written data on i/o7. an open-drain nbusy output pin provides another method of detect- ing the end of a program or erase cycle. this pin is pulled low while program and erase cycles are in progress and is released at the completion of the cycle. a toggle bit feature provides a third means of detecting the end of a program or erase cycle.
12 at91fr4081 1386c ? atarm ? 02/02 the flash memory is segmented into two memory planes. reads from one memory plane may be performed even while program or erase functions are being executed in the other memory plane. this feature enhances performance by not requiring the system to wait for a program or erase cycle to complete before a read may be performed. the flash memory is divided into 22 sectors for erase operations. to further enhance device flexibility, an erase suspend feature is offered. this feature puts the erase cycle on hold for an indefinite period and allows the user to read data from, or to write data to, any other sector within the same memory plane. there is no need to suspend an erase cycle if the data to be read is in the other memory plane. the device has the capability to protect data stored in any sector. once the data protection for a sector is enabled, the data in that sector cannot be changed while input levels lie between ground and vdd. an optional vpp pin is available to enhance program/erase times. see the at49bv/lv8011(t) 8-megabit (512k x 16/1m x 8) 3-volt only flash memory datasheet for further detail. a 6-byte command sequence (bypass unlock) allows the device to be written to directly, using single pulses on the write control lines. this mode (single-pulse programming) is exited by powering down the device or by pulsing the nrstf pin low for a minimum of 50 ns and then bringing it back to vdd. the following hardware features protect against inadvertent programming of the flash memory: vdd sense ? if vdd is below 1.8v (typical), the program function is inhibited. vdd power-on delay ? once vdd has reached the vdd sense level, the device will automatically time out 10 ms (typically) before programming. program inhibit ? holding any one of oe low, ce high or we high inhibits program cycles. noise filter ? pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle.
13 at91fr4081 1386c ? atarm ? 02/02 at91 flash uploader software all flash-based at91 devices are delivered with a pre-programmed software called the at91 flash uploader, which resides in the first sector of the embedded flash. the flash uploader allows programming to the embedded flash through a serial port. either of the on-chip usarts can be used by the flash uploader. figure 3. flash uploader flash uploader operations the flash uploader requires ncs0 to be connected to ncsf and a valid clock to be applied to mcki. the chip select line loop allows the arm core to boot from the embedded flash when the reset is de-asserted. next, the flash uploader immediately recopies itself in the internal sram and jumps into it. the following operation requires this memory resource only. external accesses are performed only to program the flash. when starting, pio input change interrupts are initialized on the rxd lines of both usarts. when an interrupt occurs, a timer counter channel is started. when the next input change is detected on the rxd line, the timer counter channel is stopped. this is how the first charac- ter length is measured and the usart can be initiated by taking into account the ratio between the device master clock speed and the actual communication baud rate speed. the programming system, then, can send commands and data following a proprietary proto- col for the flash device to be programmed. it is up to the programming system to erase and program the first sector of the flash lastly, in order to reduce, at a minimum, the risk that the flash uploader is erased and the power supply shuts down. in the event that the flash uploader is erased from the first sector while the new final applica- tion is not yet programmed, and while the target system power supply is switched off, it would lead to a non-recoverable error and the at91fr4081 could not be re-programmed by using the flash uploader. programming system atmel provides a free host loader that runs on an ibm compatible pc under windows ? 95 or windows ? 98 operating system. it can be downloaded from the atmel web site and requires only a serial cable to connect the host to the target. at91m40800 usart0 usart1 embedded flash at91f40816 target system ncsf ncs0 programming system serial port rs232 driver
14 at91fr4081 1386c ? atarm ? 02/02 communications can be selected on either com1 or com2 and the serial link speed is limited to 115200 bauds. because the serial link is the bottleneck in this configuration, the flash pro- gramming lasts 110 seconds per mbyte. programming time can be reached by using a faster programming system. an eb40 (at91 evaluation board for the x40 series microcontroller) is capable of running a serial link at up to 500 kbits/sec and can match the fastest programming allowed by the flash, for example, about 40 seconds per mbyte when the word programming becomes the bottleneck. peripherals the at91fr4081 peripherals are connected to the 32-bit wide advanced peripheral bus. peripheral registers are only word accessible. byte and half-word accesses are not supported. if a byte or a half-word access is attempted, the memory controller automatically masks the lowest address bits and generates a word access. each peripheral has a 16-kbyte address space allocated (the aic only has a 4-kbyte address space). peripheral registers the following registers are common to all peripherals: control register ? write only register that triggers a command when a one is written to the corresponding position at the appropriate address. writing a zero has no effect. mode register ? read/write register that defines the configuration of the peripheral. usually has a value of 0x0 after a reset. data registers ? read and/or write register that enables the exchange of data between the processor and the peripheral. status register ? read only register that returns the status of the peripheral. enable/disable/status registers are shadow command registers. writing a one in the enable register sets the corresponding bit in the status register. writing a one in the disable register resets the corresponding bit and the result can be read in the status register. writing a bit to zero has no effect. this register access method maximizes the efficiency of bit manipulation, and enables modification of a register with a single non- interruptible instruction, replacing the costly read-modify-write operation. unused bits in the peripheral registers must be written at 0 for upward compatibility. these bits read 0. peripheral interrupt control the interrupt control of each peripheral is controlled from the status register using the inter- rupt mask. the status register bits are anded to their corresponding interrupt mask bits and the result is then ored to generate the interrupt source signal to the advanced interrupt controller. the interrupt mask is read in the interrupt mask register and is modified with the interrupt enable register and the interrupt disable register. the enable/disable/status (or mask) makes it possible to enable or disable peripheral interrupt sources with a non-interruptible sin- gle instruction. this eliminates the need for interrupt masking at the aic or core level in real- time and multi-tasking systems. peripheral data controller the at91fr4081 has a 4-channel pdc dedicated to the two on-chip usarts. one pdc channel is dedicated to the receiver and one to the transmitter of each usart. the user interface of a pdc channel is integrated in the memory space of each usart. it contains a 32-bit address pointer register (rpr or tpr) and a 16-bit transfer counter reg- ister (rcr or tcr). when the programmed number of transfers are performed, a status bit indicating the end of transfer is set in the usart status register and an interrupt can be generated.
15 at91fr4081 1386c ? atarm ? 02/02 system peripherals ps: power-saving the power-saving feature optimizes power consumption, enabling the software to stop the arm7tdmi clock (idle mode), restarting it when the module receives an interrupt (or reset). it also enables on-chip peripheral clocks to be enabled and disabled individually, matching power consumption and application needs. aic: advanced interrupt controller the advanced interrupt controller has an 8-level priority, individually maskable, vectored interrupt controller, and drives the nirq and nfiq pins of the arm7tdmi from: the external fast interrupt line (fiq) the three external interrupt request lines (irq0 - irq2) the interrupt signals from the on-chip peripherals the aic is extensively programmable offering maximum flexibility, and its vectoring features reduce the real-time overhead in handling interrupts. the aic also features a spurious vector detection feature, which reduces spurious interrupt handling to a minimum, and a protect mode that facilitates the debug capabilities. pio: parallel i/o controller the at91fr4081 has 32 programmable i/o lines. six pins are dedicated as general-purpose i/o pins. other i/o lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. the pio controller enables generation of an interrupt on input change and insertion of a simple input glitch filter on any of the pio pins. wd: watchdog the watchdog is built around a 16-bit counter and is used to prevent system lock-up if the software becomes trapped in a deadlock. it can generate an internal reset or interrupt, or assert an active level on the dedicated pin nwdovf. all programming registers are pass- word-protected to prevent unintentional programming. sf: special function the at91fr4081 provides registers that implement the following special functions. chip identification reset status protect mode
16 at91fr4081 1386c ? atarm ? 02/02 user peripherals usart: universal synchronous/ asynchronous receiver transmitter the at91fr4081 provides two identical, full-duplex, universal synchronous/asynchronous receiver/transmitters. each usart has its own baud rate generator, and two dedicated peripheral data controller channels. the data format includes a start bit, up to 8 data bits, an optional programmable par- ity bit and up to 2 stop bits. the usart also features a receiver timeout register, facilitating variable length frame sup- port when it is working with the pdc, and a time-guard register, used when interfacing with slow remote equipment. tc: timer counter the at91fr4081 features a timer counter block that includes three identical 16-bit timer counter channels. each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. the timer counter can be used in capture or waveform mode, and all three counter channels can be started simultaneously and chained together.
17 at91fr4081 1386c ? atarm ? 02/02 ordering information table 4 . ordering information ordering code package temperature operating range AT91FR4081-33CI bga 120 industrial (-40 cto85 c)
18 at91fr4081 1386c ? atarm ? 02/02 packaging information figure 4. 120-ball ball grid array package drawing table 5 . thermal resistance data symbol parameter condition package typ units ja junction-to- ambient thermal resistance still air 120-bga 36.6 c/w jc junction-to-case thermal resistance 120-bga 11 table 6 . device and 120-ball bga package maximum weight 626 mg 12345678910111213141516 a b c d e f g h j k k j h g f e d c b a 1.00 0.15 + ? 15.00 0.15 + ? 9.00 0.15 + ? 17.00 0.15 + ? 1.00 0.15 + ? 11.00 0.15 + ? 0.51 (120) 1.70 max 0.41 max top view bottom view side view all dimensions in millimeters 12345678910111213141516
19 at91fr4081 1386c ? atarm ? 02/02 soldering profile table 7 gives the recommended soldering profile from j-std-20. small packages may be subject to higher temperatures if they are reflowed in boards with larger components. in this case, small packages may have to withstand temperatures of up to 235 c, not 220 c(irreflow). recommended package reflow conditions depend on package thickness and volume. see table 8. notes: 1. the packages are qualified by atmel by using ir reflow conditions, not convection or vpr. 2. by default, the package level 1 is qualified at 220 c (unless 235 c is stipulated). 3. the body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability. a maximum of three reflow passes is allowed per component. table 7 . soldering profile convection or ir/convection vpr average ramp-up rate (183 c to peak) 3 c/sec. max. 10 c/sec. preheat temperature 125 c25 c 120 sec. max temperature maintained above 183 c 60sec.to150sec. time within 5 c of actual peak temperature 10 sec. to 20 sec. 60 sec. peak temperature range 220 +5/-0 cor 235 +5/-0 c 215 to 219 cor 235 +5/-0 c ramp-down rate 6 c/sec. 10 c/sec. time 25 c to peak temperature 6 min. max table 8 . recommended package reflow conditions (1,2,3) parameter temperature convection 220 +5/-0 c vpr 215 to 219 c ir/convection 220 +5/-0 c
20 at91fr4081 1386c ? atarm ? 02/02 document details title at91fr4081 datasheet literature number 1386s revision history version a publication date: sep-00 version b publication date: jul-01 version c publication date: 29-jan-02 revisions since previous version page: 10 added information to section internal memories page: 17 changed table 3 page:18 added table 5 page:19 added section soldering profile
printed on recycled paper. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company ? s standard warranty whichisdetailedinatmel ? s terms and conditions located on the company ? s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel ? s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 casa postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia atmel asia, ltd. room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan atmel japan k.k. 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 microcontrollers atmel corporate 2325 orchard parkway san jose, ca 95131 tel 1(408) 436-4270 fax 1(408) 436-4314 atmel nantes la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards atmel rousset zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 atmel smart card ics scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive atmel heilbronn theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 atmel colorado springs 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom atmel grenoble avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 1386c ? atarm ? 02/02 0m atm el ? is the registered trademark of atmel. ibm ? is a registered trademark of ibm corporation; windows ? is a registered trademark of microsoft corporation; arm ? ,thumb ? and arm powered ? are registered trademarks of arm ltd.; arm7tdmi ? is the trademark of arm ltd. other terms and product names may be the trademarks of others.

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